SPI status
| BUS_BUSY | SPI bus is busy. The bus is considered busy (‘1’) during an ongoing transaction. For Motorola and National submodes, the busy bit is ‘1’, when the slave selection is activated. For TI submode, the busy bit is ‘1’ from the time the preceding/coinciding slave select is activated for the first transmitted data frame, till the last MOSI/MISO bit of the last data frame is transmitted. |
| SPI_EC_BUSY | Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are reliable. |
| CURR_EZ_ADDR | SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is ‘1’), as clock domain synchronization is not performed in the design. |
| BASE_EZ_ADDR | SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable, as clock domain synchronization is not performed in the design. |